EDN

I2C-Based Real Time Clock / Calendar – RTL Design and Verification

Designed the main architecture of ASIC IC PCF8583 by Philips Semiconductors. It involved writing time and calendar properties sent by I2C master onto an I2C based slave RAM.
Semiconductor Engineering

Modification Of An Existing E-Graph Based RTL Optimization Tool As A Formal Verification Assistant

A technical paper titled “Datapath Verification via Word-Level E-Graph Rewriting” was published by researchers at Intel Corporation and Imperial College London. “Formal verification of datapath ...
Electronic Design

RTL Design Verification Tool Eliminates Learning Curve

Designed to be easy to use by eliminating the learning curve normally associated with formal register transfer level (RTL) design verification technology, BlackTie is offered as a functional checker ...
Semiconductor Engineering

Formal Verification of Security Properties On RTL Designs

A technical paper titled “RTL Verification for Secure Speculation Using Contract Shadow Logic” was published by researchers at Princeton University, MIT CSAIL, and EPFL. “Modern out-of-order ...